Samsung will launch advanced 3D chip packaging technology SAINT in 2024

Nov 15,2023

As the semiconductor component manufacturing process approaches the physical limit, advanced packaging technologies that allow multiple components to be combined and packaged into a single electronic component, thereby improving semiconductor performance, have become key to competition. Samsung is preparing its own advanced packaging solution to compete with TSMC's CoWoS packaging technology.

It is reported that Samsung plans to launch advanced 3D chip packaging technology SAINT (Samsung Advanced Interconnection Technology) in 2024, which can integrate the memory and processor of high-performance chips such as AI chips in a smaller size package. Samsung SAINT will be used to develop various solutions, offering three types of packaging technologies, including:

SAINT S - Used for vertically stacking SRAM storage chips and CPUs

SAINT D - Used for vertically encapsulating core IPs such as CPU, GPU, and DRAM

SAINT L - Used for stacking application processors (APs)

Samsung has passed validation testing, but plans to expand its service scope later next year after further testing with customers, with the goal of improving the performance of data center AI chips and built-in AI function mobile application processors.

If everything goes according to plan, Samsung SAINT has the potential to gain some market share from competitors, but it remains to be seen whether companies such as NVIDIA and AMD will be satisfied with the technology they provide.

According to reports, Samsung is vying for a large number of HBM memory orders, which will continue to support Nvidia's next generation Blackwell AI GPUs. Samsung recently launched Shinebolt "HBM3e" memory and won orders for AMD's next-generation Instact accelerator, but compared to NVIDIA, which controls about 90% of the artificial intelligence market, this order proportion is much lower. It is expected that the HBM3 orders of the two companies will be booked and sold out before 2025, and the market demand for AI GPUs remains strong.

As the company shifts from single-chip design to chiplet based architecture, advanced packaging is the direction forward.

TSMC is expanding its CoWoS facilities and investing heavily in testing and upgrading its own 3D stacking technology SoIC to meet the needs of customers such as Apple and Nvidia. TSMC announced in July this year that it would invest 90 billion New Taiwan Dollars (approximately 2.9 billion US dollars) to build an advanced packaging plant; As for Intel, it has started using its new generation of 3D chip packaging technology, Fooveros, to manufacture advanced chips.

UMC, the world's third largest wafer foundry, has launched the Wafer to Wafer (W2W) 3D IC project, utilizing silicon stacking technology to provide cutting-edge solutions for efficiently integrating memory and processors.

UMC stated that the W2W 3D IC project is ambitious, collaborating with advanced packaging factories and service companies such as ASE, Winbond, Faraday, and Cadence Design Systems to fully utilize 3D chip integration technology to meet the specific needs of edge AI applications.
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